1. Field of the Invention
The present invention relates to a characteristic evaluation semiconductor device (TEG: test element group), and more particularly, it relates to a memory cell evaluation semiconductor device for evaluating a memory cell, a method of fabricating the same and a memory cell evaluation method.
2. Description of the Background Art
The operation of a memory cell included in a DRAM is now described with reference to FIGS. 51 to 54. A capacitor which is formed by a counter electrode CP and a storage node electrode SN stores charges, thereby writing data in the memory cell (FIG. 51). The capacitor holds the charges stored therein, thereby holding the data in the memory cell (FIG. 52). In practice, however, the charges may move through a dielectric film provided between the counter electrode CP and the storage node electrode SN to result in the so-called capacitor leakage (FIG. 53) or may move between the capacitor and a part enclosing the same to result in the so-called junction leakage (FIG. 54). Due to a leakage current resulting from such movement of the charges, the memory cell cannot hold but loses the data. Therefore, the DRAM rewrites the data in the memory cell before losing the same. The DRAM periodically performs this operation, which is called a refresh operation.
The recent DRAM is generally applied to a portable appliance such as a portable telephone, a mobile computer or the like, and must have small power consumption. However, the DRAM consumes power every refresh operation. Therefore, the DRAM maximizes the interval (hereinafter referred to a refresh execution interval) for performing the refresh operation while preventing loss of the data, thereby reducing the number of times for executing the refresh operation and reducing power consumption of the DRAM.
In order to prevent data loss in a number of memory cells provided in the DRAM, a number of memory cell samples are prepared for deciding the refresh execution interval on the basis of a sample exhibiting the shortest time up to loss of written data.
FIG. 55 is a graph statistically showing the relation between data loss and the refresh execution interval. Referring to FIG. 55, the horizontal axis shows an average refresh execution interval and the longitudinal axis shows the data loss probability. When the refresh execution interval is within the range of 0 to T0, the data loss probability is zero, i.e., no data is lost in any memory cell of the DRAM. When the refresh execution interval exceeds T0, on the other hand, data is lost at least in one memory cell of the DRAM. Referring to FIG. 55, the most efficient refresh execution interval for reducing power consumption is T0.
Two methods are employable for extending the refresh execution interval. The first method, which is adapted to entirely move the curve as shown in FIG. 56, can be implemented by improving the aforementioned leakage current as to all memory cells provided in the DRAM (this method is hereinafter referred to as "large pattern improvement"). The second method, which is adapted to zero the data loss probability around T0 as shown in FIG. 57, can be implemented by improving a specific memory cell having an inferior characteristic as to the leakage current, for example, among the memory cells provided in the DRAM (this method is hereinafter referred to as "small pattern improvement). It is effective for the small pattern improvement to statistically evaluate a number of memory cells, as shown in the graph of FIG. 55.
The difference between these two methods is now described with reference to FIGS. 58 to 60. FIGS. 58 and 59 are conceptual diagrams showing the structure of the DRAM comprising an aggregate DM of a number of memory cells MC. Referring to FIGS. 58 and 59, black squares denote defective memory cells MC. FIG. 60 is a graph showing the relation between voltages applied to the aggregate DM and leakage currents. Referring to FIG. 60, symbols ISA, ISL and IL represent an average leakage current caused in each memory cell MC, a leakage current of each defective memory cell MC and a leakage current flowing out from the aggregate DM respectively.
In the aforementioned large pattern improvement, a test in a development stage is easy to perform since the test is made on the overall aggregate DM shown in FIG. 58 by checking the leakage current IL flowing out from the same. However, the leakage current ISL, which is included in the leakage current IL, is undetectable.
In the small pattern improvement, on the other hand, it is difficult to perform a test, which is made on each memory cell MC shown in FIG. 59 by checking the leakage current IS flowing out from the same. In order to find out a memory cell MC having an inferior characteristic as to the leakage current, further, the respective ones of the memory cells MC forming the aggregate DM must be tested. However, the leakage current ISL is detectable.
Thus, the small pattern improvement is not employed in general due to the difficulty of the test as compared with the large pattern improvement.
However, electric fields in the memory cells tend to increase following the increased scale of the recent DRAM, and it is difficult to extend the refresh execution interval through the large pattern improvement.
Therefore, the refresh execution interval may be extended by the small pattern improvement. However, it is impossible to make the best use of the small pattern improvement, since there is no method of evaluating a single memory cell.